The present disclosure relates to an internal voltage detection circuit and an internal voltage generation device using the same, and more particularly to an internal voltage detection circuit for generating and supplying a pulse signal of a period varying with temperature in a self-refresh operation of a DRAM, and an internal voltage generation device using the same.
In general, a dynamic random access memory (DRAM) comprises a plurality of memory cells, each of which is composed of one cell transistor and one data storage capacitor. A read operation and a write operation are basically performed with respect to the memory cells of the DRAM, constructed in the above manner. First, the read operation will hereinafter be described in association with, as an example, the case where a high level (1.6V) is stored in a memory cell.
At the time that a word line is activated to a high voltage Vpp level, a cell transistor is turned on, resulting in charge sharing occurring between a data storage capacitor and a bit line capacitor. This charge sharing in turn results in a potential difference or gap ΔV being generated between a bit line BIT LINE and an inverted bit line BITB LINE. This potential difference is developed by a sensing operation of a bit line sense amplifier. Then, charges on the bit line BIT LINE and inverted bit line BITB LINE are transferred to outside of the DRAM cell over input/output lines lio, liob, gio and giob. This series of operations is collectively called the read operation.
Notably, a transistor has a characteristic that its threshold voltage is higher when temperature is lower. Owing to this characteristic, when the memory cell operates at low temperature, the cell transistor is turned on incompletely due to a raised threshold voltage thereof, leading to inadequate charge sharing between the data storage capacitor and the bit line capacitor. In otherwords, at low temperature, a potential barrier of the cell-transistor rises, so that a relatively small amount of charges is transferred from the data storage capacitor to the bit line capacitor. This results in a phenomenon that the potential difference ΔV between the bit line BIT LINE and the inverted bit line BITB LINE becomes small. When the bit line sense amplifier is operated under the condition that the potential difference ΔV between the bit line BIT LINE and the inverted bit line BITB LINE is formed to such a small degree, the bit line sense amplifier may fail to recognize the potential difference correctly, so that it may reversely develop the potentials of the bit line BIT LINE and inverted bit line BITB LINE, leading to a fail phenomenon that, for example, high-level data on the bit line is misrecognized as low-level data. This fail phenomenon in the low-temperature operation of the memory cell similarly occurs in the write operation.